Conversion of zest to linux-on-litex-vexriscv so it can be built with fully open source toolchain and run on open source hardware lika radiona ulx3s.
- C 22.6%
- VHDL 17.7%
- Python 17.6%
- Verilog 15.7%
- Tcl 10.4%
- Other 15.9%
| Filename | Latest commit message | Latest commit date |
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Bengt Sjölén
47822ccfd7
ECP5 (ULX3S/icepi) via OSS CAD Suite; also XC7 via Vivado and Sipeed Tang via Gowin IDE and potentially other litex targets when the board has enough logic, DRAM, and HDMI. |
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| deps | ||
| docs | ||
| drivers | ||
| hdl | ||
| linux | ||
| scripts | ||
| setup | ||
| vivado | ||
| xdc | ||
| zest_litex | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| LICENSE | ||
| mkdocs.yml | ||
| README-litex.md | ||
| README.md | ||
| requirements.txt | ||
zeST - An implementation of an Atari ST in VHDL
Copyright (c) 2019-2025 by François Galea (fgalea à free.fr)
This is a complete implementation of an Atari ST in VHDL, which targets cheap Xilinx Zynq-7000-based prototyping boards.
Its main features are:
- Cycle accuracy, including CPU and display (demos work great!)
- HDMI for video and audio output
- USB for keyboard, mouse input, joysticks, MIDI
- "Accurate enough" floppy drive emulation with support for any format the disk controller can write (not read)
- ACSI hard drive emulation
- Switchable wakestates
- Optional 50 MHz turbo mode
External hardware cores zeST is based on:
- Jorge Cwik's fx68k processor core, a cycle-accurate 68000 processor implementation
- Tsuyoshi Hasegawa's HD63701 compatible processor core, used as the keyboard processor
- John Kent's 6850 compatible ACIA core
All other components have been redesigned from scratch.
zeST is distributed under the GNU General Public License v3 licence. See the LICENSE file or https://www.gnu.org/licenses/gpl-3.0.html for more details.
Contributors
- François Galea
- George Nakos